Way back in 1985, the first MIPS cpu was released, a modern take on high performance computing. In 2021, that door was closed. Let’s go back and look at the crazy story of MIPS.


Welcome to another episode of Brain Dump. I’m Josh, standing in for today’s video. Let’s dive right in.


Leading Up to MIPS


Before the 1970s, CPU design was really focused on functionality rather than form. Every computing firm was making their own processors for their own computers, pushing their own programming languages and operating systems. Oftentimes, the CPU’s architecture was designed to make the job of compilers easier, where the intended programming language functions could map almost directly to silicon, or through a layer of microcode underneath the exposed interface.


CPU instructions created to do complex jobs could make software development easier, but that didn’t come for free. Those instructions would require a lot more logic to implement, which translates into larger dies, more heat, and difficulty raising clock speeds to advance performance. In the 1970s, engineers were kicking around the idea of simplifying the cpu’s instruction set,  reducing it to the smaller building blocks of logic and letting the compiler handle stringing them together. This concept was coined as RISC, or reduced instruction set computer, and the old way was named CISC, or complex instruction set computer.


In 1979, an engineer named David Patterson went to Berkeley and started the Berkeley RISC program, funded by a grant from DARPA. David and his team had the opportunity to research and develop in a pure fashion, without a direct requirement of corporate profitability. This allowed them to focus on not just getting things done but getting them done better or more cleanly. The team would go on to create two processor designs, creatively named RISC and RISC 2. You’ve probably never heard of them, but they were the direct basis of the SPARC processors later produced by Sun.


In 1981, John Hennessey at Stanford would create a similar project for grad students, and in 1983 had a chip of his own. His team would aggressively push for higher clock speeds, using pipelines to allow their cpu to effectively split execution into stages. The pipeline splits execution into steps. Instead of doing one instruction from start to finish before moving to the next, the pipeline could start the setup of the next instruction just one step behind the current one. All of the components of the processor could be potentially engaged at the same time, working on the different stages of execution for the next instruction or instructions down the line. They called this project MIPS, or Microprocessor without Interlocked Pipeline Stages.


The advantages of MIPS were easily apparent in practice, with clock speeds reaching well above contemporary CISC processors. It even turned out that many complex operations were actually faster, clock for clock, broken down on a RISC processor than running as a single instruction on a CISC one. 


MIPS Computing Systems


In 1984, John and his colleagues were seeing impressive performance compared to existing commercial offerings, and would break off from Stanford to form MIPS Computing Systems. In 1986 they released their first product, the MIPS R2000. It featured a 5 stage pipeline and a clock speed up to 15 megahertz at launch. The major competitors of the day were Digital’s VAX, Motorola’s 68000, and Intel’s 80386, all of which were CISC designs. The R2000 was the beginning of a flood of RISC processors, from HP, Sun, IBM, Motorola, Digital, Intel, and others.


MIPS Computing Systems would create their own Unix workstation line, but it would see limited commercial success. However, the MIPS processors would find homes in systems from several other vendors, notably Silicon Graphics, and Digital. Digital had been working on a RISC processor of their own but was plagued with internal struggles over competing with their own VAX line. They would use the R2000 and future chips before eventually launching their own Alpha processor in 1991. Silicon Graphics would become not only the largest user of MIPS processors, but also a co-developer going forward.


In 1988, MIPS would release the R3000, based on the same instruction set but operating at higher clock speeds up to 33 megahertz, and introducing a system of coprocessors allowing manufacturers to add more functionality directly attached to the CPU. This processor did well in the workstation and server market, but also showed in a few strange places. You could find the R3000 in arcades, in the games Area 51 and maximum force from Atari, or Konami’s popular Dance Dance Revolution games. LSI would work with MIPS to create MIPS16, an extension of the ISA allowing for 16 bit processing modes, and would shrink this cpu into an embedded SOC that could be found in all sorts of places. And for most of you, the most accessible way to touch an R3000 based system is with Sony’s Playstation and Playstation 2 game consoles.


The work with LSI would be critical a few years later, as it really got MIPS into the embedded space. But let’s not get too far ahead of ourselves.


In 1989, the R6000 was announced. This introduced a new version of the MIPS architecture, creatively called MIPS 2. The R6000 was an impressive performer but suffered from high costs, supply problems from the chip fabricator, and long lead times, resulting in little commercial success.


Total MIPS Domination


1991 rolls around and we get another update, the R4000 featuring the 3rd revision of the architecture. Of course it’s called MIPS 3, and it features 64 bit design, a longer 8 stage pipeline, and clock speeds up to 100 megahertz. Significant efforts were made to push the R4000 into personal computing, but the performance advantages above Intel’s 80486 alone weren’t enough to compete with the Wintel platform, especially with the Pentium line on the horizon. SGI however had a very different customer base, and the R4000 was a massive success for them. In 1991, when the bleeding edge gaming console was the Super Nintendo and Microsoft Windows was still firmly 16 bit and sub-50 megahertz, SGI would sell you a 100 megahertz 64 bit workstation with 3d hardware accelerated graphics. Insane.


Silicon Graphics Inc


In 1992, SGI liked MIPS so much, they bought the company.


In 1993, an update to the R4000 was released, the R4400. This was almost purely a speed bump, increasing cache sizes and boosting clock speeds from a previous maximum of 100 megahertz all the way up to as much as 250 megahertz. Again, the primary user was Silicon graphics, but many other vendors would embrace the r4400 for their flagship servers and workstations. Microsoft would even build a port of their Windows NT workstation product for some of these systems, giving users a non-Unix option designed to integrate with their existing desktop computer infrastructure.


MIPS 3 would eventually be embraced not only by the server and workstation market, but again by embedded computing systems and gaming systems including the hugely successful Nintendo 64.


MIPS 4 came in 1994, and the R8000 was the first new chip released under SGI’s ownership. Hugely powerful, but also very expensive, 10% of the top 500 supercomputers in the world in 1994 would use the R8000. Proving that you can’t judge a processor solely by clock speed, the 75 to 90 megahertz R8000 was far more powerful than the much higher clocked R4400. Outside of scientific computing it wasn’t exactly a hit, but MIPS was on top of the world.


The Beginning Of The End


1996 would bring the R10000, intended to replace both the R4400 on the low end and the R8000 on the high end with a single processor. The new R10k featured a superscalar design with out of order execution, giving yet another big performance boost and enabling another big clock speed boost, up to 195 megahertz. But yet again availability and cost were big issues as fabs struggled to produce them. On top of tha,t a run of the R10k chips was found to be faulty and roughly 10000 of them were recalled.


The next several years would bring derivative processors of that R10k, with no significant architectural changes. Instead there were ever smaller manufacturing processes, support for newer memory systems such as DDR, and tweaks made to cache sizes and speeds. SGI would continue these regular updates until 2004, when they released the R16000A with a clock speed up to 900 megahertz. They announced one more chip, the R18000, but sadly it was canceled before completion. What happened?


Well, in 1998, SGI announced that their next servers would be based on Intel’s new Itanium architecture, and split off MIPS back into its own company. This would be a story repeated with many other vendors who met a similar fate of losing market relevance. Meanwhile, the newly independent MIPS Technologies shifted their focus away from high performance servers. 


Going Tiny


Of course, MIPS had a pretty good history in the embedded space already. Changing the focus from massive servers and high performance graphics workstations to highly integrated, low wattage SoCs wasn’t as big of a change as you might think. They would split the architecture into two segments, developing both 32 and 64 bit designs, and license them to chip makers such as Broadcom, LSI, Ralink, and Ingenic. Those manufacturers would often combine the MIPS core with additional features such as network accelerators and camera or video processors, creating dozens of variations for specific applications. The 64 bit designs would be used in high end gear, such as network processors on internet backbone routers. The 32 bit versions would be found in tons of consumer and mid tier gear. For a while, MIPS was back on top, dominating the market for things like wifi routers and network connected security cameras.


Losing Again


Ownership of MIPS, the company, eventually went to Wave Computing, who tried to bring MIPS back into relevance with forgettable open source initiatives. They would release the final iteration of the MIPS architecture, revision 5, in 2012. Many factors joined together to end the era of MIPS, but the biggest hit was simply an inability to compete with ARM. ARM’s ecosystem was exploding in popularity after becoming the de-facto standard for mobile phones and the Android operating system. 


ARM was constantly innovating and working to expand beyond gadgets and into the datacenter, whileMIPS was mostly powering cheap network cameras and cheap routers… ARM would eventually take over in the home wifi router market as well. Wave would announce in 2021 that development of the MIPS architecture had officially ceased, and that their future efforts would focus on the up and coming RISC-5 architecture.


Oh, you think, how the mighty have fallen. But it wasn’t just MIPS, so many of the names from this story are just memories. Intel had an attractive story and nearly every independent computer vendor ate it up, dropping their in-house processor teams to go with the big engine that couldn’t.


Market consolidation, particularly when combined with every vendor offering essentially the same Itanium platform, made most of these former giants redundant. Intel’s big plan was to hold 64 bit home computing hostage by making Itanium the only path forward, but AMD surprised the world with the AMD64 extensions for x86 that made Itanium irrelevant for nearly all use cases. Intel would announce the discontinuation of Itanium in 2019, more than 2 years before MIPS; amusingly it had outlived its replacement.


MIPS in 2023


Of course, you can still buy brand new devices with MIPS processor cores in them today. To the best of my knowledge, only Ingenic are still developing and manufacturing MIPS based chips, but they’re still plentiful and easy to find. Other videos on this channel cover hacking these inexpensive devices to release the inner MIPS server, with basic electronics tools and skills you can get your very own MIPS Linux box for as little as 10 bucks… Sadly you won’t be booting SGI’s IRIX operating system on it, but they’re a great way to get started in hardware hacking and embedded Linux.


The End


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